LTC1408CUH#PBF;LTC1408IUH#PBF;LTC1408CUH;LTC1408CUH#TRPBF;LTC1408IUH#TRPBF;中文规格书,Datasheet资料

with Shutdown

DESCRIPTIOThe LTC®1408 is a 14-bit, 600ksps ADC with six simulta-neously sampled differential inputs. The device drawsonly 5mA from a single 3V supply, and comes in a tiny 32pin (5mm × 5mm) QFN package. A SLEEP shutdownfeature lowers power consumption to 6µW. The combina-tion of low power and tiny package makes the LTC1408suitable for portable applications.The LTC1408 contains six separate differential inputs thatare sampled simultaneously on the rising edge of theCONV signal. These six sampled inputs are thenconverted at a rate of 100ksps per channel.The 90dB common mode rejection allows users toeliminate ground loops and common mode noise bymeasuring signals differentially from the source.The device converts 0V to 2.5V unipolar inputs differen-tially, or ±1.25V bipolar inputs also differentially,depending on the state of the BIP pin. Any analog inputmay swing rail-to-rail as long as the differential inputrange is maintained.The conversion sequence can be abbreviated to convertfewer than six channels, depending on the logic state ofthe SEL2, SEL1 and SEL0 inputs.The serial interface sends out the six conversion results in96 clocks for compatibility with standard serial interfaces.FEATURES■■■■■■■■■■■■■600ksps ADC with 6 Simultaneously SampledDifferential Inputs100ksps Throughput per Channel76dB SINADLow Power Dissipation: 15mW3V Single Supply Operation2.5V Internal Bandgap Reference, Can be Overdrivenwith External Reference3-Wire Serial InterfaceInternal Conversion Triggered by CONVSLEEP (6µW) Shutdown ModeNAP (3.3mW) Shutdown Mode0V to 2.5V Unipolar, or ±1.25V Bipolar DifferentialInput Range90dB Common Mode RejectionTiny 32-Pin (5mm × 5mm) QFN PackageUAPPLICATIOS■■■■Multiphase Power MeasurementMultiphase Motor ControlData Acquisition SystemsUninterruptable Power Supplies, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6084440, 6522187.BLOCK DIAGRACH5–CH5+CH4–CH4+2120191817CH3–CH3+CH2–CH2+CH1–CH1+CH0–CH0+10µFVCC16151412131110987624––S AND H––––S AND HS AND HS AND HS AND HS AND H600ksps14-BIT ADCMUXTIMINGLOGIC3032VREF10µF2329BIP262728312.5VREFERENCEGND3322http://oneic.com/

UW3VVDD2514-BIT LATCH 014-BIT LATCH 114-BIT LATCH 214-BIT LATCH 314-BIT LATCH 414-BIT LATCH 5OVDD3VSD00.1µF2OGND++++++THREE-STATESERIALOUTPUTPORT31CONVSCKDGNDSEL2SEL1SEL01408 TA011408fa

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LTC1408ABSOLUTE(Notes 1, 2)AXIURATIGSPACKAGE/ORDERIFORATIOTOP VIEW161514131211109CH4+17CH4–Supply Voltage (VDD, VCC, OVDD)..............................4VAnalog Input Voltage(Note 3)...................................– 0.3V to (VDD + 0.3V)Digital Input Voltage....................– 0.3V to (VDD + 0.3V)Digital Output Voltage..................– 0.3V to (VDD + 0.3V)Power Dissipation..............................................100mWOperation Temperature RangeLTC1408C...............................................0°C to 70°CLTC1408I............................................–40°C to 85°CStorage Temperature Range.................–65°C to 125°CORDER PARTNUMBER876321CH1–CH1+GNDCH0–CH0+OVDDOGNDSDOCH3–CH3+CH2–CH2+GNDGNDGNDGND18GND19CH5+20CH5–LTC1408CUHLTC1408IUHQFN PART MARKING14082133GND22VREF23VCC242526272829303132VDDBIPSEL2SEL1SEL0QFN PACKAGE32-PIN (5mm × 5mm) PLASTIC QFNTJMAX = 125°C, θJA = 34°C/WEXPOSED PIN IS GND (PAD 33)MUST BE SOLDERED TO PCBOrder Options Tape and Reel: Add #TRLead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBFLead Free Part Marking: http://www.linear.com/leadfree/Consult LTC Marketing for parts specified with wider operating temperature ranges.CO VERTER CHARACTERISTICSPARAMETERResolution (No Missing Codes)Integral Linearity ErrorOffset ErrorOffset Match from CH0 to CH5Range ErrorRange Match from CH0 to CH5Range TempcoThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V, VDD = VCC = 3V.CONDITIONS●DGNDCONVSCKMIN14–3–4.5–3–12–5●●TYP±0.5±1±0.5±2±1±15±1MAX34.53125UNITSBitsLSBmVmVmVmVppm/°Cppm/°C(Note 5)(Note 4)(Note 4)Internal Reference (Note 4)External Reference●A ALOG I PUTSYMBOLPARAMETERVINVCMIINCINtACQtAPtJITTERtSKCMRRThe ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V, VDD = VCC = 3V.CONDITIONS2.7V ≤ VDD ≤ 3.3V(Note 8)●MINTYP0 to 2.50 to VDDMAXUNITSVVAnalog Differential Input Range (Notes 3, 8, 9)Analog Common Mode + DifferentialInput RangeAnalog Input Leakage CurrentAnalog Input CapacitanceSample-and-Hold Acquisition TimeSample-and-Hold Aperture Delay TimeSample-and-Hold Aperture Delay Time JitterChannel to Channel Aperture SkewAnalog Input Common Mode Rejection Ratio1133910.3200(Note 6)●fIN = 100kHz, VIN = 0V to 3VfIN = 10MHz, VIN = 0V to 3V–83–671408fa

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UµApFnsnspspsdBdBWUUWWWUUULTC1408

DY A IC ACCURACYSYMBOLSINADPARAMETERSignal-to-Noise PlusDistortion RatioThe ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V, VDD = VCC = 3V.CONDITIONS100kHz Input Signal300kHz Input Signal100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V300kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V100kHz First 5 Harmonics300kHz First 5 Harmonics100kHz Input Signal300kHz Input Signal0.625VP-P, 833kHz into CH0+, 0.625VP-P, 841kHz into CH0–.Bipolar Mode. Also Applicable to Other ChannelsVREF = 2.5V (Note 17)VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15)S/(N + D) ≥ 68dB, Bipolar Differential Input●THDSFDRIMDUUUI TER AL REFERE CE CHARACTERISTICSPARAMETERVREF Output VoltageVREF Output TempcoVREF Line RegulationVREF Output ResistanceVREF Settling TimeCONDITIONSIOUT = 0DIGITAL I PUTS A D DIGITAL OUTPUTS

SYMBOLVIHVILIINCINVOHVOLIOZCOZISOURCEISINKPARAMETERHigh Level Input VoltageLow Level Input VoltageDigital Input CurrentDigital Input CapacitanceHigh Level Output VoltageLow Level Output VoltageHi-Z Output Leakage DOUTHi-Z Output Capacitance DOUTOutput Short-Circuit Source CurrentOutput Short-Circuit Sink CurrentVOUT = 0V, VDD = 3VVOUT = VDD = 3VCONDITIONSVDD = 3.3VVDD = 2.7VVIN = 0V to VDDThe ● denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at TA = 25°C. VDD = VCC = 3V.MIN●●●http://oneic.com/

UUWU MIN73TYP76767979–90–869086–800.7505MAXUNITSdBdBdBdBdBdBdBdBdBLSBRMSMHzMHzTotal HarmonicDistortionSpurious FreeDynamic RangeIntermodulationDistortionCode-to-CodeTransition NoiseFull Power BandwidthFull Linear Bandwidth●–80TA = 25°C. VDD = VCC = 3V.MINTYP2.5156000.22MAXUNITSVppm/°CµV/VΩmsVDD = 2.7V to 3.6V, VREF = 2.5VLoad Current = 0.5mATYPMAX0.6±10UNITSVVµApFVVVµApFmAmA2.45VDD = 3V, IOUT = –200µAVDD = 2.7V, IOUT = 160µAVDD = 2.7V, IOUT = 1.6mAVOUT = 0V and VDD●●●2.52.90.050.4±10120151408fa

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LTC1408

POWER REQUIRE E TSSYMBOLVDD, VCCIDD + ICCPARAMETERSupply VoltageSupply CurrentThe ● denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC= 3V.CONDITIONSActive Mode, fSAMPLE = 600kspsNap ModeSleep ModeActive Mode with SCK, fSAMPLE = 600ksps●●PDPower DissipationThe ● denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25°C. VDD = 3V.SYMBOLfSAMPLE(MAX)tTHROUGHPUTtSCKtCONVt1t2t3t4t5t6t7t8t9t10t11PARAMETERMaximum Sampling Frequency per Channel(Conversion Rate)Minimum Sampling Period (Conversion + Acquisiton Period)Clock PeriodConversion TimeMinimum Positive or Negative SCLK Pulse WidthCONV to SCK Setup TimeSCK Before CONVMinimum Positive or Negative CONV Pulse WidthSCK to Sample ModeCONV to Hold Mode96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)Minimum Delay from SCK to Valid Bits 0 Through 11SCK to Hi-Z at SDOPrevious SDO Bit Remains Valid After SCKVREF Settling Time After Sleep-to-Wake Transition(Note 16)(Notes 6, 17)(Note 6)(Notes 6, 10)(Note 6)(Note 6)(Note 6)(Notes 6, 11)(Notes 6, 7, 13)(Notes 6, 12)(Notes 6, 12)(Notes 6, 12)(Notes 6, 14)CONDITIONS●●●WUTI I G CHARACTERISTICSNote 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliabilty and lifetime.Note 2: All voltage values are with respect to ground GND.Note 3: When these pins are taken below GND or above VDD, they will beclamped by internal diodes. This product can handle input currents greaterthan 100mA below GND or greater than VDD without latchup.Note 4: Offset and range specifications apply for a single-ended CH0+ –CH5+ input with CH0– – CH5– grounded and using the internal 2.5Vreference.Note 5: Integral linearity is tested with an external 2.55V reference and isdefined as the deviation of a code from the straight line passing throughthe actual endpoints of a transfer curve. The deviation is measured fromthe center of quantization band. Linearity is tested for CH0 only.Note 6: Guaranteed by design, not subject to test.Note 7: Recommended operating conditions.Note 8: The analog input range is defined for the voltage differencebetween CHx+ and CHx–, x = 0–5.http://oneic.com/

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UWMIN2.7TYP51.12.015MAX3.671.915UNITSVmAmAµAmWMIN100TYPMAXUNITSkHz66710096230441.24586221000010000nsnsSCLK cyclesnsnsnsnsnsnsnsnsnsnsmsNote 9: The absolute voltage at CHx+ and CHx– must be within this range.Note 10: If less than 3ns is allowed, the output data will appear one clockcycle later. It is best for CONV to rise half a clock before SCK, whenrunning the clock at rated speed.Note 11: Not the same as aperture delay. Aperture delay (1ns) is thedifference between the 2.2ns delay through the sample-and-hold and the1.2ns CONV to Hold mode delay.Note 12: The rising edge of SCK is guaranteed to catch the data comingout into a storage latch.Note 13: The time period for acquiring the input signal is started by the96th rising clock and it is ended by the rising edge of CONV.Note 14: The internal reference settles in 2ms after it wakes up from Sleepmode with one or more cycles at SCK and a 10µF capacitive load.Note 15: The full power bandwidth is the frequency where the output codeswing drops by 3dB with a 2.5VP-P input sine wave.Note 16: Maximum clock period guarantees analog performance duringconversion. Output data can be read with an arbitrarily long clock period.Note 17: The conversion process takes 16 clocks for each channel that isenabled, up to 96 clocks for all 6 channels.1408fa

LTC1408

TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°CSINAD, ENOBs vs Frequency77747112.51211.51110.510UNIPOLAR SINGLEENDEDBIPOLARDIFFERENTIAL0.1110FREQUENCY (MHz)1001408 G01SINAD (dB)686562595653THD (dB)3rdTHD (dB)SFDR vs Input Frequency1049286BIPOLAR DIFFERENTIAL7675747372OUTPUT MAGNITUDE (dB)SFDR (dB)SNR (dB)807468625650440.1110FREQUENCY (MHz)1001408 G04UNIPOLAR SINGLE ENDED98kHz Bipolar Sine Wave 4096Point FFT Plot, 100 ksps0–10–20OUTPUT MAGNITUDE (dB)OUTPUT MAGNITUDE (dB)–30–40–50–60–70–80–90–100–110–120OUTPUT MAGNITUDE (dB)–30–40–50–60–70–80–90–100–110–1200102030FREQUENCY(kHz)40501408 G07http://oneic.com/

UWTHD, 2nd and 3rdvs Input Frequency–44–50–56–625 HARMONIC THD2ndUNIPOLAR SINGLE ENDED–44–50–56–62–68–74–80–86–92–98–1040.1110FREQUENCY (MHz)1001408 G02THD, 2nd and 3rdvs Input FrequencyBIPOLAR SINGLE ENDEDVCM = 1.5VENOBS (bits)–68–74–80–86–92–98–1045 HARMONIC THD3rd9.598.52nd0.1110FREQUENCY (MHz)1001408 G03SNR vs Input Frequency0BIPOLARDIFFERENTIAL98kHz Unipolar Sine Wave 4096Point FFT Plot, 100 ksps–10–20–30–40–50–60–70–80–90–100–110–120717069686766650.1UNIPOLARSINGLE ENDED110FREQUENCY (MHz)1001408 G050102030FREQUENCY(kHz)40501408 G06591kHz Bipolar Differential SineWave 4096 Point FFT Plot,100 ksps0–10–200–10–20–30–40–50–60–70–80–90–100–1100102030FREQUENCY(kHz)40501408 G08101kHz Unipolar Single EndedSine Wave 4096 Point FFT Plot,625 ksps–120062.5125188FREQUENCY(kHz)2503131408 G091408fa

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LTC1408

TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C610kHz Unipolar Single EndedInput Sine Wave 4096 Point FFT,625ksps0–10–20OUTPUT MAGNITUDE (dB)–20–30MAGNITUDE (dB)DIFFERENTIAL LINEARITY (LSB)–30–40–50–60–70–80–90–100–110–120062.5125188FREQUENCY(kHz)2503131408 G10Integral Linearity End Point Fit forCH0 with Internal 2.5VReference, Unipolar Mode4.03.21.00.8INTEGRAL LINEARITY (LSB)INTEGRAL LINEARITY (LSB)2.41.60.80–0.8–1.6–2.4–3.2–4.004096122888192OUTPUT CODE163841408 G13DIFFERENTIAL LINEARITY (LSB)Full Scale Signal Response30–3–6MAGNITUDE (dB)CMRR (dB)–12–15–18–21–24–27–3010100FREQUENCY (MHz)10001408 G16–60–80–100PSSR (dB)–9http://oneic.com/

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UW833kHz into CH0 +, 841kHz intoCH0 –, 588ksps Bipolar Mode4096 Point FFT0–101.00.80.60.40.20–0.2–0.4–0.6–0.8–1.0

Differential Linearity for CH0 withInternal 2.5V Reference,Unipolar Mode–40–50–60–70–80–90–100–110–120050200100150FREQUENCY(kHz)2503001408 G1104096

122888192

OUTPUT CODE

16384

1408 G12

Differential Linearity for CH0 withInternal 2.5V Reference,Differential Input in Bipolar Mode4.03.22.41.60.80–0.8–1.6–2.4–3.2–4.004096122888192OUTPUT CODE163841408 G14Integral LinearIty End Point Fit0.60.40.20–0.2–0.4–0.6–0.8–1.004096122888192OUTPUT CODE163841408 G15CMRR vs Frequency0–20–400–20–40–60–80–100CROSSTALK vs Frequency–1201001k10k100k1M10M100M1GFREQUENCY (Hz)1408 G20–1201001k10k100k1M10M100M1GFREQUENCY (Hz)1408 G211408fa

LTC1408

TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°CSimultaneous Step at all 6 Channelsfrom 25Ω Source SamplingFrequency = 625kspsInput Frequency = 625.0381MHz163841433612288CH0 THRU CH5RISINGOUTPUT CODE1024081926144409620480–505CH0 THRU CH5FALLING1510TIME (ns)20251408 G22CMRR (dB)PI FU CTIO SSDO (Pin 1): Three-State Serial Data Output. Each set ofsix output data words represent the six analog inputchannels at the start of the previous conversion. Data forCH0 comes out first and data for CH5 comes out last. Eachdata word comes out MSB first.OGND (Pin 2): Ground Return for SDO Currents. This padmust always be within 300mV of the ground plane poten-tial.OVDD (Pin 3): Power Supply for the SDO Pin. OVDD mustbe no more than 300mV higher than VDD and can bebrought to a lower voltage to interface to low voltage logicfamilies. The unloaded high state at SDO is at the potentialof OVDD.CH0+ (Pin 4): Non-Inverting Channel 0. CH0+ operatesfully differentially with respect to CH0– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.CH0– (Pin 5): Inverting Channel 0. CH0– operates fullydifferentially with respect to CH0+ with a –2.5V to 0V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. Theseground pins must be tied directly to the solid ground planeunder the part. Analog signal currents flow through theseconnections.CH1+ (Pin 7): Non-Inverting Channel 1. CH1+ operatesfully differentially with respect to CH1– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.CH1– (Pin 8): Inverting Channel 1. CH1– operates fullydifferentially with respect to CH1+ with a –2.5V to 0V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.CH2+ (Pin 10): Non-Inverting Channel 2. CH2+ operatesfully differentially with respect to CH2– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.CH2– (Pin 11): Inverting Channel 2. CH2– operates fullydifferentially with respect to CH2+ with a –2.5V to 0V, or±1.25V differential swing and a 0V to VDD absoluteinput range.http://oneic.com/

UWPSRR vs Frequency0–20–40–60–80–100–1201001k10k100k1M10M100M1GFREQUENCY (Hz)1408 G23

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LTC1408

PI FU CTIO SCH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operatesfully differentially with respect to CH3– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absoluteinput range.CH3– (Pin 15): Inverting Channel 3. CH3– operates fullydifferentially with respect to CH3+ with a –2.5V to 0V, or±1.25V differential swing and a 0V to VDD absoluteinput range.CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operatesfully differentially with respect to CH4– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absolute inputrange.CH4– (Pin 18): Inverting Channel 4. CH4– operates fullydifferentially with respect to CH4+ with a –2.5V to 0V, or±1.25V differential swing and a 0V to VDD absolute inputrange.CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operatesfully differentially with respect to CH5– with a 0V to 2.5V,or ±1.25V differential swing and a 0V to VDD absolute inputrange.CH5– (Pin 21): Inverting Channel 5. CH5– operates fullydifferentially with respect to CH5+ with a –2.5V to 0V, or±1.25V differential swing and a 0V to VDD absolute inputrange.GND (PIN 22): Analog Ground for Reference. Analogground must be tied directly to the solid ground planeunder the part. Analog signal currents flow through thisconnection. The 10µF reference bypass capacitor shouldbe returned to this pad.VREF (Pin 23): 2.5V Internal Reference. Bypass to GNDand a solid analog ground plane with a 10µF ceramiccapacitor (or 10µF tantalum in parallel with 0.1µF ce-ramic). Can be overdriven by an external reference voltagebetween 2.55% and VDD, VCC.VCC (Pin 24): 3V Positive Analog Supply. This pin supplies3V to the analog section. Bypass to the solid analogground plane with a 10µF ceramic capacitor (or 10µFtantalum) in parallel with 0.1µF ceramic. Care should betaken to place the 0.1µF bypass capacitor as close toPin 24 as possible. Pin 24 must be tied to Pin 25.VDD (Pin 25): 3V Positive Digital Supply. This pin supplies3V to the logic section. Bypass to DGND pin and solidanalog ground plane with a 10µF ceramic capacitor (or10µF tantalum in parallel with 0.1µF ceramic). Keep inmind that internal digital output signal currents flowthrough this pin. Care should be taken to place the 0.1µFbypass capacitor as close to Pin 25 as possible. Pin 25must be tied to Pin 24.SEL2 (Pin 26): Most significant bit controlling thenumber of channels being converted. In combination withSEL1 and SEL0, 000 selects just the first channel (CH0) forconversion. Incrementing SELx selects additionalchannels(CH0–CH5) for conversion. 101, 110 or 111select all 6 channels for conversion. Must be kept in a fixedstate during conversion and during the subsequent con-version to read data.SEL1 (Pin 27): Middle significance bit controlling thenumber of channels being converted. In combination withSEL0 and SEL2, 000 selects just the first channel (CH0) forconversion. Incrementing SELx selects additionalchannels for conversion. 101, 110 or 111 select all 6channels (CH0–CH5) for conversion. Must be kept in afixed state during conversion and during the subsequentconversion to read data.SEL0 (Pin 28): Least significant bit controlling thenumber of channels being converted. In combination withSEL1 and SEL2, 000 selects just the first channel (CH0) forconversion. Incrementing SELx selects additionalchannels for conversion. 101, 110 or 111 select all 6channels (CH0–CH5) for conversion. Must be kept in afixed state during conversion and during the subsequentconversion to read data.BIP (Pin 29): Bipolar/Unipolar Mode. The input differen-tial range is 0V – 2.5V when BIP is LOW, and it is ±1.25when BIP is HIGH. Must be kept in fixed state duringconversion and during subsequent conversion to readdata. When changing BIP between conversions the fullacquisition time must be allowed before starting the nextconversion. The output data is in 2’s complementformat for bipolar mode and straight binary format forunipolar mode.http://oneic.com/

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LTC1408

PI FU CTIO SCONV (Pin 30): Convert Start. Holds the six analog inputsignals and starts the conversion on the rising edge. Twopulses with SCK in fixed high or fixed low state starts Napmode. Four or more pulses with SCK in fixed high or fixedlow state starts Sleep mode.DGND (Pin 31): Digital Ground. This ground pin must betied directly to the solid ground plane. Digital input signalcurrents flow through this pin.SCK (Pin 32): External Clock Input. Advances the conver-sion process and sequences the output data at SD0 (Pin1)on the rising edge. One or more pulses wake from sleepor nap power saving modes. 16 clock cycles are neededfor each of the channels that are activated by SELx (Pins26, 27, 28), up to a total of 96 clock cycles needed toconvert and read out all 6 channels.EXPOSED PAD (Pin 33): GND. Must be tied directly to thesolid ground plane.BLOCK DIAGRA 0.1µF10µFVCC24CH0+43VVDD25LTC1408CH0–CH1+CH1–CH2+CH2–CH3+CH3–CH4+CH4–CH5+CH5–http://oneic.com/

WUUU+S & H567–+S & H10–+S & H11121314–MUX600ksps14-BIT ADC+S & H14-BIT LATCH 014-BIT LATCH 114-BIT LATCH 214-BIT LATCH 314-BIT LATCH 414-BIT LATCH 5OVDD3VTHREE-STATESERIALOUTPUTPORT3SD01OGND20.1µF151617–+S & HTIMINGLOGIC3032CONVSCK181920–+S & H21–2.5VREFERENCEEXPOSED PAD33GND2210µFBIPSEL2SEL1SEL0VREF232926272831DGND1408 BD1408fa

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LTC1408

TI I G DIAGRA SLTC1408 Timing Diagramhttp://oneic.com/

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WUW1408fa

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LINEAR-TECHNOLOGYLTC1408CUH#PBFLTC1408CUH#TRPBF

LTC1408IUH#PBFLTC1408IUH#TRPBF

LTC1408CUHDC887A